Latest

• ActiveN: A Scalable and Flexibly-programmable Event-driven Neuromorphic Processor
• DTrans: A Dataflow-transformation FPGA Accelerator with Nonlinear-operators fusion aiming for the Generative Model
• A Row Decomposition-based Approach for Sparse Matrix Multiplication on GPUs
• Research on General-purpose Brain-Inspired Computing Systems
• MAICC : A Lightweight Many-core Architecture with In-Cache Computing for Multi-DNN Parallel Inference
• FABLE: A Development and Computing Framework for Brain-inspired Learning Algorithms
• Multi-objective optimization for Floating Point Mix-Precision Tuning.
• ENLARGE: An Efficient SNN Simulation Framework on GPU Clusters
• Performance optimization method of sparse lower trigonometric equation solver on multi-core CPU architecture
• Simulation device and simulation method
• GaBAN: a generic and flexibly programmable vector neuro-processor on FPGA
• Method and device for realizing brain-like calculation based on vector instruction set
• Accelerating Neural Network Training with Processing-in-Memory GPU
• A review of basic software for brain-inspired computing
• Program performance prediction method, neural network training method and application
• Sparse matrix storage method, vector calculation method and electronic equipment
• Polyhedral-Based Compilation Framework for In-Memory Neural Network Accelerators
• Regu2D: Accelerating Vectorization of SpMV on Intel Processors through 2D-partitioning and Regular Arrangement
• Approximate computing method based on memristors
• A Proposal of Software-Hardware Decoupling Hardware Design Method for Brain-Inspired Computing
• Towards "general purpose" brain-inspired computing system
• A Reduced Architecture for ReRAM-Based Neural Network Accelerator and Its Software Stack
• XB-SIM*: A Simulation Framework for Modeling and Exploration of ReRAM-Based CNN Acceleration Design
• High Performance Simulation of Spiking Neural Network on GPGPUs
• A system hierarchy for brain-inspired computing
• ERA-LSTM: An Efficient ReRAM-Based Architecture for Long Short-Term Memory
• Hardware implementation of spiking neural networks on FPGA
• Towards artificial general intelligence with hybrid Tianjic chip architecture
• Training and Software Simulation for ReRAM-Based LSTM Neural Network Acceleration
• FPSA: A Full System Stack Solution for Reconfigurable ReRAM-based NN Accelerator Architecture
• A Unified Framework for Training, Mapping and Simulation of ReRAM-Based Convolutional Neural Network Acceleration
• Programmable neural network trojan for pre-trained feature extractor
• TETRIS: TilE-matching the TRemendous Irregular Sparsity
• Hardware neural network conversion method, computing device, compiling method and neural network software and hardware collaboration system
• Bridge the Gap between Neural Networks and Neuromorphic Hardware with a Neural Network Compiler
• In-Place Irregular Computation for Message-Passing Chip-Multiprocessors
• Hardware support for message-passing in chip multi-processors
• Hardware neural network conversion method, computing device, software and hardware cooperative system
• Parallel Turing Machine, a Proposal
• NEUTRAMS: Neural network transformation and co-design under neuromorphic hardware constraints
• Optimized Mapping Spiking Neural Networks onto Network-on-Chip
• Neural network transformation under hardware constraints
• Modelling Spiking Neural Network from the Architecture Evaluation Perspective
• Software-Based Lightweight Multithreading to Overlap Memory-Access Latencies of Commodity Processors
• A Cloud Gaming System Based on User-Level Virtualization and Its Resource Scheduling